multi-phase

CMOS digital duty cycle correction circuit for multi-phase clock

by

CMOS digital duty cycle correction circuit for multi-phase clock by Young-Chan Jang, Seung-Jun Bae, Hong-June Park.

A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications the multi-phase clock and standby mode. Two integrators are used detector to eliminate effect of reference voltage variations. The adjusted 50/spl plusmn/0.25% throughout input range from 20% 80% at frequency 1.25 GHz. 0.18 /spl mu/m CMOS technology this work.

Read CMOS digital duty cycle correction circuit for multi-phase clock on OA.mg